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STM8AF6346ITD データシート(PDF) 70 Page - STMicroelectronics |
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STM8AF6346ITD データシート(HTML) 70 Page - STMicroelectronics |
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70 / 95 page  Electrical characteristics STM8AF6366 70/95 DS12343 Rev 2 Figure 37. SPI timing diagram where slave mode and CPHA = 0 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. Figure 38. SPI timing diagram where slave mode and CPHA = 1 1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD. 3. Values based on design simulation and/or characterization results, and not tested in production. 4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. ai14135b NSS input tSU(NSS) tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) MISO OUTPUT MOSI INPUT tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB OUT LSB IN BIT 1 IN |
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