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AT25QL641 データシート(PDF) 18 Page - Renesas Technology Corp

部品番号 AT25QL641
部品情報  SPI Serial Flash Memory with Dual I/O, Quad I/O, QPI Support
PDF  80 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25QL641 データシート(HTML) 18 Page - Renesas Technology Corp

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DS-AT25QL641-130 Rev. G
Page 18
Sep 14, 2022
© 2022 Renesas Electronics
AT25QL641 Datasheet
8.
Commands
The SPI command set of the AT25QL641 consists of thirty eight basic commands and the QPI command set of
the AT25QL641 consists of thirty one basic commands that are fully controlled through the SPI bus (see Table 8
through Table 11). Commands are initiated with the falling edge of Chip Select (CS). The first byte of data clocked
into the input pins (SI or I/O [3:0]) provides the command code. Data on the SI input is sampled on the rising edge
of clock with most significant bit (MSB) first.
Commands are completed with the rising edge of edge CS. All read commands can be completed after any
clocked bit. However, all commands that Write, Program or Erase must complete on a byte (CS driven high after
the full 8 bits has been clocked) otherwise the command is terminated. This feature further protects the device
from inadvertent writes. Additionally, while the memory is being programmed or erased, or when the Status
Register is being written, all commands except for Read Register are ignored until the program or erase cycle has
completed.
Table 7. Manufacturer and Device Identification
ID code
Command
Manufacturer ID
Renesas Electronics
1Fh
90h, 92h, 94h, 9Fh
Device ID
AT25QL641
16h
90h, 92h, 94h, ABh
Memory Type ID
SPI / QPI
43h
9Fh
Capacity Type ID
64M
17h
9Fh



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