ASM330LHB datasheet(108/131 Pages) STMICROELECTRONICS

108 / 131 page

11.39

EMB_FUNC_ODR_CFG_C (60h)

Machine learning core output data rate configuration register (R/W)

Table 227. EMB_FUNC_ODR_CFG_C register

0(1)

MLC_ODR1

MLC_ODR0

0(1)

1(2)

0(1)

1(2)

1. This bit must be set to 0 for the correct operation of the device.

2. This bit must be set to 1 for the correct operation of the device.

Table 228. EMB_FUNC_ODR_CFG_C register description

MLC_ODR[1:0]

Machine learning core ODR configuration:

(00: 12.5 Hz;

01: 26 Hz (default);

10: 52 Hz;

11: 104 Hz)

11.40

EMB_FUNC_INIT_B (67h)

Embedded functions initialization register (R/W)

Table 229. EMB_FUNC_INIT_B register

0(1)

MLC_INIT

0(1)

FSM_INIT

1. This bit must be set to 0 for the correct operation of the device.

Table 230. EMB_FUNC_INIT_B register description

MLC_INIT

Machine learning core initialization request. Default value: 0

FSM_INIT

FSM initialization request. Default value: 0

11.41

MLC0_SRC (70h)

Machine learning core source register (R)

Table 231. MLC0_SRC register

MLC0_

SRC_7

MLC0_

SRC_6

MLC0_

SRC_5

MLC0_

SRC_4

MLC0_

SRC_3

MLC0_

SRC_2

MLC0_

SRC_1

MLC0_

SRC_0

Table 232. MLC0_SRC register description

MLC0_SRC_[7:0]

Output value of MLC0 decision tree

ASM330LHB

EMB_FUNC_ODR_CFG_C (60h)

DS13773 - Rev 7

page 108/131

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