L9969X datasheet(41/70 Pages) STMICROELECTRONICS

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Figure 28. SPI data line management

If both the NSS were to be asserted and the communication did not have problems such as those indicated in

the following paragraphs, the action will be taken in both bridges. The NSS1 signal has priority over the NSS2,

therefore, the value that will be reported on the data output SO will depend on how the two signals are driven.

3.2.7.2

SPI communication

A SPI communication always starts with an SPI instruction sent from the controller to the H-bridge.

During a write cycle the controller sends the data after the SPI instruction, beginning with the MSB.

During a reading cycle, after having received the SPI instruction, the H-bridge sends the corresponding data to

the controller, also starting with the MSB.

In general, depending on the specific application four different frame types are supported (see the table below).

The frames-types are defined by the number of bits being transferred during an active slave-select phase (falling

SCK-edges during NSS = low).

Table 25. Frame Types

Instruction

Data

Standard:

16-bit frame

8 bits

Extended_2 is not used in H-bridge

Extended_3 is not used in H-bridge

Burst frame types are not used in H-bridge

L9969x

Functional behavior in detail

DS14029 - Rev 3

page 41/70

L9969X データシート(PDF) 41 Page - STMicroelectronics