HCS163MS

FN3087 Rev 1.00

Page 2 of 9

September 1995

Functional Block Diagram

CP

P

MR

T2

Q2

CP

P

MR

T1

Q1

CP

P

MR

T0

Q0

CP

P

MR

T3

Q3

Q3

Q2

12

Q1

13

14

Q0

11

P0

3

P1

4

P2

5

P3

6

PE

7

TE

10

9

SPE

1

MR

2

CP

15

TC

Q0 Q1

Q2 Q3

VCC

TE

TE

D0

D1

D2

D3

TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

MR

CP

PE

TE

SPE

PN

QN

TC

Reset (clear)

l

XXXX

L

L

Parallel Load

h (Note 3)

X

X

l

l

L

L

h (Note 3)

X

X

l

h

H

(Note 1)

Count

h (Note 3)

h

h

h (Note 3)

X

Count

(Note 1)

Inhibit

h (Note 3)

X

l (Note 2)

X

h (Note 3)

X

Qn

(Note 1)

h (Note 3)

X

X

l (Note 2)

h (Note 3)

X

Qn

L

H = HIGH Voltage Level

L = LOW Voltage Level

h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition

l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition

X = Immaterial

q = Lower case letter indicate the state of the referenced output prior to the LOW-to-HIGH clock transition

= LOW-to-HIGH clock transition

NOTES:

1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HLLH for 162 and HHHH for 163)

2. The HIGH-to-LOW transition of PE or TE on the 54/74163 and 54/74160 should only occur while CP is high for conventional operation

3. The LOW-to-HIGH transition of SPE or MR on the 54/74163 should only occur while CP is high for conventional operation