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AD5378ABC データシート(PDF) 9 Page - Analog Devices

部品番号 AD5378ABC
部品情報  32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC
PDF  28 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD5378ABC データシート(HTML) 9 Page - Analog Devices

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Preliminary Technical Data
AD5378
Rev. PrA | Page 9 of 28
PARALLEL INTERFACE
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; AGND = DGND = DUTGND = 0 V; VREF(+) = +5 V;
VREF(−) = −3.5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 6.
Parameter1, ,
2 3
Limit at TMIN to TMAX
Unit
Description
t0
4.5
ns min
REG0, REG1, Address to WR Rising Edge Setup Time.
t1
4.5
ns min
REG0, REG1, Address to WR Rising Edge Hold Time.
t2
10
ns min
CS Pulse Width Low.
t3
10
ns min
WR Pulse Width Low.
t4
0
ns min
CS to WR Falling Edge Setup Time.
t5
0
ns min
WR to CS Rising Edge Hold Time.
t6
4.5
ns min
Data to WR Rising Edge Setup Time.
t7
4.5
ns min
Data to WR Rising Edge Hold Time.
t8
20
ns min
WR Pulse Width High.
t9
240
ns min
Minimum WR Cycle Time (Single-Channel Write).
t104
0/30
ns min/max
WR Rising Edge to BUSY Falling Edge.
t114
330
ns max
BUSY Pulse Width Low (Single-Channel Update). See Table 11.
t12
0
ns min
BUSY Rising Edge to WR Rising Edge.
t13
30
ns min
WR Rising Edge to LDAC Falling Edge.
t14
20
ns min
LDAC Pulse Width Low.
t154
150
ns typ
BUSY Rising Edge to DAC Output Response Time.
t16
20
ns min
LDAC Rising Edge to WR Rising Edge.
t17
0
ns min
BUSY Rising Edge to LDAC Falling Edge.
t18
100
ns typ
LDAC Falling Edge to DAC Output Response Time.
t19
20/30
µs typ/ max
DAC Output Settling Time.
t20
10
ns min
CLR Pulse Width Low.
t21
350
ns max
CLR/RESET Pulse Activation Time.
t22
10
ns min
RESET Pulse Width Low.
t23
120
µs max
RESET Time Indicated by BUSY
Low.
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3 See
.
Figure 6
4 Measured with load circuit in Figure 2.



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