MPC962305 REVISION 8 3/15/16

5

©2016 Integrated Device Technology, Inc.

MPC962305 Data Sheet

LOW-COST, 3.3V ZERO DELAY BUFFEr

APPLICATIONS INFORMATION

Figure 1. Output-to-Output Skew tSK(O)

Figure 2. Static Phase Offset Test Reference

Figure 3. Output Duty Cycle (DC)

Figure 4. Device-to-Device Skew

Figure 5. Cycle-to-Cycle Jitter

Figure 6. Output Transition Time Test Reference

The pin-to-pin skew is defined as the worst case difference in propagation

delay between any similar delay path within a single device

VCC

1.4 V

GND

VCC

1.4 V

GND

t5

VCC

VCC 2

GND

VCC

VCC 2

GND

t6

CCLK

FB_IN

The time from the PLL controlled edge to the non-controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

VCC

1.4 V

GND

t2

t1

DC = t2/t1 x 100%

VCC

VCC 2

GND

VCC

VCC 2

GND

t7

DEVICE 1

DEVICE 2

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

tN

tJ = |tN–tN+1|

tN+1

t4

t3

VCC = 3.3 V

2.0

0.8