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ADIS16201/PCB データシート(PDF) 5 Page - Analog Devices

部品番号 ADIS16201/PCB
部品情報  Programmable Dual-Axis
PDF  32 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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ADIS16201/PCB データシート(HTML) 5 Page - Analog Devices

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Data Sheet
ADIS16201
Rev. C | Page 5 of 32
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2.
Parameter
Description
Min1
Typ
Max
Unit
fSCLK
Fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)
0.01
2.5
MHz
Normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)
0.01
1.0
MHz
tDATARATE
Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fs ≥ 1024 Hz)
32
μs
tDATARATE
Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fs ≤ 910 Hz)
42
μs
tSTALL
Stall period, fast mode, SMPL_PRD ≤ 0x07 (fs ≥ 1024 Hz)
10
μs
tSTALL
Stall period, normal mode, SMPL_PRD ≥ 0x08 (fs ≤ 910 Hz)
12
μs
tcs
Chip select to clock edge
48.8
ns
tDAV
Data output valid after SCLK edge
100
ns
tDSU
Data input setup time before SCLK rising edge
24.4
ns
tDHD
Data input hold time after SCLK rising edge
48.8
ns
tDF
Data output fall time
5
12.5
ns min
tDR
Data output rise time
5
12.5
ns min
tSFS
CS high after SCLK edge
5
ns typ
1 Guaranteed by design, not tested.
TIMING DIAGRAMS
CS
SCLK
tDATA RATE
tSTALL = tDATA RATE – 16/fSCLK
tSTALL
Figure 2. SPI Chip Select Timing
CS
SCLK
DOUT
DIN
1
2
3
4
5
6
15
16
W/R
A5
A4
A3
A2
D2
MSB
DB14
D1
LSB
DB13
DB12
DB10
DB11
DB2
LSB
DB1
tCS
tSFS
tDAV
tDHD
tDSU
Figure 3. SPI Timing
(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)



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