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ADG2108BCPZ-R2 データシート(PDF) 10 Page - Analog Devices

部品番号 ADG2108BCPZ-R2
部品情報  I2C CMOS 8 횞 10 Unbuffered Analog Switch Array with Dual/Single Supplies
PDF  28 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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ADG2108BCPZ-R2 データシート(HTML) 10 Page - Analog Devices

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ADG2108
Rev. 0 | Page 10 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
NC
VDD
X9
X8
X7
X6
X5
X4
X1
NC
NC
NC
X3
X2
X0
VSS 1
2
3
4
5
6
7
8
32
31
30
29 28
27
26
25
24
23
22
21
20
19
18
17
9
10
11
13141516
12
PIN 1
INDICATOR
ADG2108
10 × 8
TOP VIEW
(Not to Scale)
Exposed Paddle Soldered to VSS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions1
Pin No.
Mnemonic
Description
1
VSS
Negative Power Supply in a Dual-Supply Application. For single-supply applications, this pin
should be tied to GND.
2 to 4, 23
NC
No Connect.
5 to 8,
17 to 22
X0 to X9
Can be inputs or outputs.
9 to 16
Y0 to Y7
Can be inputs or outputs.
24
VDD
Positive Power Supply Input.
25
VL
Logic Power Supply Input.
26
SDA
Digital I/O. Bidirectional open drain data line. External pull-up resistor required.
27
SCL
Digital Input, Serial Clock Line. Open drain input that is used in conjunction with SDA to clock data
into the device. External pull-up resistor required.
28
A0
Logic Input. Address pin that sets the least significant bit of the 7-bit slave address.
29
A1
Logic Input. Address pin that sets the second least significant bit of the 7-bit slave address.
30
A2
Logic Input. Address pin that sets the third least significant bit of the 7-bit slave address.
31
RESET
Active Low Logic Input. When this pin is low, all switches are open, and appropriate registers are cleared to 0.
32
GND
Ground. Reference point for all circuitry on the ADG2108.
1 It is recommended that the exposed paddle be soldered to VSS to improve heat dissipation and crosstalk.



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