IDTTM/ICSTM

64-pin CK505 w/Fully Integrated Voltage Regulator

1118N—05/19/11

Advance Information

ICS9LPR501

64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR

18

Datasheet

Byte 22 CPU M/N Programming

Bit

Pin

Name

Description

Type

01

Default

7

N Div bit 8

PLL 1 M/N Programming

RW

--

X

6

N Div bit 9

(Intel PLL1 CPU)

RW

--

X

5M Div Bit 5

RW

--

X

4M Div Bit 4

RW

--

X

3M Div Bit 3

RW

--

X

2M Div Bit 2

RW

--

X

1M Div Bit 1

RW

--

X

0M Div Bit 0

RW

--

X

Byte 23 CPU M/N Programming

Bit

Pin

Name

Description

Type

01

Default

7

N Div bit 7

PLL 1 M/N Programming

RW

--

X

6

N Div bit 6

(Intel PLL1 CPU)

RW

--

X

5

N Div bit 5

RW

--

X

4

N Div bit 4

RW

--

X

3

N Div bit 3

RW

--

X

2

N Div bit 2

RW

--

X

1

N Div bit 1

RW

--

X

0N Div Bit 0

RW

--

X

Bytes 24-62 Reserved

Byte 63 Special Power Management Features (Rev P Silicon and Higher)

Bit

Pin

Name

Description

RW

0

1

Default

7

Reserved

RW

0

6

Reserved

RW

0

5

Reserved

RW

0

4

Reserved

RW

0

3

Reserved

RW

0

2

Reserved

RW

0

1

SATA PLL

Power Management Feature

RW

off

on

Note

0

XTAL PD Control

Controls XTAL on/off in legacy PD

RW

off

on

1

Note: Default is "off" for Rev P Silicon and higher.

*Accessing any SMBus bytes not shown in the datasheet could result in incorrect clock functions.