8

MC68L300EC16/D

NOTES:

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum

allowable tXcyc period is reduced when the duty cycle of the external clock varies. The relationship between ex-

ternal clock input duty cycle and minimum tXcyc is expressed:

Minimum tXcyc period = minimum tXCHL / (50% – external clock input duty cycle tolerance).

3. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the relative

loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS to fall outside

the limits shown in specification 9.

4. If multiple chip selects are used, CS width negated (specification 15) applies to the time from the negation of a

heavily loaded chip select to the assertion of a lightly loaded chip select. The CS width negated specification be-

tween multiple chip selects does not apply to chip selects being used for synchronous ECLK cycles.

5. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on fast

cycle reads. The user is free to use either hold time.

6. Maximum value is equal to (tcyc / 2) + 25 ns.

7. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data setup

time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored. The data

must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle. BERR must

satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock cycle.

8. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles

of the current operand transfer are complete.

9. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specification

47A).

10. After external RESET negation is detected, a short transition period (approximately 2) tcyc elapses, then the SIM

drives RESET low for 512 tcyc.

11. External assertion of the RESET input can overlap internally-generated resets. To insure that an external reset

is recognized in all cases, RESET must be asserted for at least 590 CLKOUT cycles.

12. External logic must pull RESET high during this period in order for normal MCU operation to begin.

46A

R/W Width Asserted (Fast Write or Read Cycle)

tRWAS

90

—

ns

47A

Asynchronous Input Setup Time

BR, BGACK, DSACK[1:0], BERR, AVEC, HALT

tAIST

5—

ns

47B

Asynchronous Input Hold Time

tAIHT

15

—

ns

48

DSACK[1:0] Asserted to BERR, HALT Asserted9

tDABA

—30

ns

53

Data Out Hold from Clock High

tDOCH

0—

ns

54

Clock High to Data Out High Impedance

tCHDH

—28

ns

55

R/W Asserted to Data Bus Impedance Change

tRADC

40

—

ns

70

Clock Low to Data Bus Driven (Show Cycle)

tSCLDD

029

ns

71

Data Setup Time to Clock Low (Show Cycle)

tSCLDS

15

—

ns

72

Data Hold from Clock Low (Show Cycle)

tSCLDH

10

—

ns

73

BKPT Input Setup Time

tBKST

15

—

ns

74

BKPT Input Hold Time

tBKHT

10

—

ns

75

Mode Select Setup Time

tMSS

20

—

tcyc

76

Mode Select Hold Time

tMSH

0—

ns

77

RESET Assertion Time10

tRSTA

4—

tcyc

78

RESET Rise Time11,12

tRSTR

—10

tcyc

Table 6 16.78 MHz AC Timing (Continued)

(V

DD

and V

DDSYN

= 3.0 to 3.6Vdc, V

SS

= 0 Vdc, T

A

= T

L

to T

H)

1

Num

Characteristic

Symbol

Min

Max

Unit

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com