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ICS1893AFILF データシート(PDF) 116 Page - Renesas Technology Corp

部品番号 ICS1893AFILF
部品情報  3.3-V 10Base-T/100Base-TX Integrated PHYceiver
PDF  137 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS1893AFILF データシート(HTML) 116 Page - Renesas Technology Corp

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ICS1893AF, Rev D 10/26/04
October, 2004
116
Chapter 10
DC and AC Operating Conditions
ICS1893AF Data Sheet - Release
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
10.5.3
Timing for Receive Clock (RXCLK) Pins
Table 10-10 lists the significant time periods for signals on the Receive Clock (RXCLK) pins for the various
interfaces. Figure 10-4 shows the timing diagram for the time periods.
Figure 10-4.
Receive Clock Timing Diagram
Table 10-10.
MII Receive Clock Timing
Time
Period
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
RXCLK Duty Cycle
–
35
50
65
%
t2a
RXCLK Period
100M MII (100Base-TX)
–
40
–
ns
t2b
RXCLK Period
10M MII (10Base-T)
–
400
–
ns
RXCLK
t1
t2



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