ICS1893CFILFT datasheet(39/127 Pages) RENESAS

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Chapter 6 Functional Blocks

ICS1893CF, Rev. K, 05/13/10

May, 2010

ICS1893CF Data Sheet Rev. J - Release

When an ICS1893CF detects a reversed signal polarity on its Twisted-Pair Receiver pins and the Auto

Polarity-Inhibit bit is also logic zero (enabled), the ICS1893CF (1) automatically corrects the data stream

and (2) sets its Polarity Reversed bit (bit 18.14) to logic one, to indicate to the STA that this situation exists.

Bit 18.14 is a latching high (LH) bit. (For more information on latching high and latching low bits, see

Section 7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)

Note: The ICS1893CF will not complete the Auto-MDIX function for an inverted polarity cable. This

is a rare event with modern manufactured cables. Full Auto-Negotiation and Auto Polarity

Correction will complete when the Auto-MDIX function is disabled. Software control for the

Auto-MDIX function is available in MDIO Register 19 Bits 9:8.

6.5.14 10Base-T Operation: Isolation Transformer

The 10Base-T Isolation Transformer operates the same as the 100Base-TX Isolation Transformer. In fact,

in a typical ICS1893CF application they are the same unit. For more information, see Section 6.4.7,

“100Base-TX Operation: Isolation Transformer”.

6.6 Functional Block: Management Interface

As part of the MAC Interface, the ICS1893CF provides a two-wire serial management interface which

complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used to

exchange control, status, and configuration information between a Station Management entity (STA) and

the physical layer device (PHY). The PHY and STA exchange this data through a pre-defined set of

management registers. The ISO/IEC standard specifies the following components of this serial

management interface:

• A set of registers (Section 6.6.1, “Management Register Set Summary”)

• The frame structure (Section 6.6.2, “Management Frame Structure”)

• The protocol

In compliance with the ISO/IEC specification, the ICS1893CF implementation of the serial management

interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the

exchange of data. These pins remain active in all ICS1893CF MAC Interface modes (that is, the 10/100

MII, 100M Symbol, and 10M Serial interface modes).

6.6.1 Management Register Set Summary

The ICS1893CF implements a Management Register set that adheres to the ISO/IEC standard. This

Control and Status registers and the ISO/IEC ‘Extended’ registers as well as some ICS-specific registers.

6.6.2 Management Frame Structure

The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the

exchange of configuration, control, and status data between a PHY, such as an ICS1893CF, and an STA.

All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange

data through a pre-defined register set.

The ICS1893CF complies with the ISO/IEC defined Management Frame Structure and protocol. This

structure supports both read and write operations. Table 6-1 summarizes the Management Frame

Structure.

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