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AM29BDS128HE8 データシート(PDF) 84 Page - SPANSION

部品番号 AM29BDS128HE8
部品情報  128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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AM29BDS128HE8 データシート(HTML) 84 Page - SPANSION

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Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
D A TA
SH EE T
AC CHARACTERISTICS
Wait State Decoding Addresses:
A14, A13, A12 = “111”
⇒ Reserved
A14, A13, A12 = “110”
⇒ Reserved
A14, A13, A12 = “101”
⇒ 5 programmed, 7 total
A14, A13, A12 = “100”
⇒ 4 programmed, 6 total
A14, A13, A12 = “011”
⇒ 3 programmed, 5 total
A14, A13, A12 = “010”
⇒ 2 programmed, 4 total
A14, A13, A12 = “001”
⇒ 1 programmed, 3 total
A14, A13, A12 = “000”
⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.
Figure 48.
Example of Wait States Insertion
Data
AVD#
OE#
CLK
12
3
4
5
D0
D1
01
6
2
7
3
total number of clock cycles
following AVD# falling edge
Rising edge of next clock cycle
following last wait state triggers
next burst data
number of clock cycles
programmed
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