IDT™ / ICS™ SAS/SATA CLOCK GENERATOR

14

ICS843241BG REV. A AUGUST 20, 2008

ICS843241

FEMTOCLOCKS™ SAS/SATA CLOCK GENERATOR

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in

Figure 6.

To calculate worst case power dissipation into the load, use the following equations which assume a 50

Ω load, and a termination

voltage of V

CC

- 2V.

•

For logic high, V

OUT

= V

OH_MAX

= V

CC_MAX

– 0.9V

(V

CC_MAX

- V

OH_MAX

) = 0.9V

•

For logic low, V

OUT

= V

OL_MAX

= V

CC_MAX

– 1.7V

(V

CC_MAX

- V

OL_MAX

) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V

OH_MAX

– (V

CC_MAX

- 2V))/R

L

] * (V

CC_MAX

- V

OH_MAX

) = [(2V - (V

CC_MAX

- V

OH_MAX

))/R

L

] * (V

CC_MAX

- V

OH_MAX

) =

[(2V - 0.9V)/50

Ω] * 0.9V = 19.8mW

Pd_L = [(V

OL_MAX

– (V

CC_MAX

- 2V))/R

L

] * (V

CCO_MAX

- V

OL_MAX

) = [(2V - (V

CC_MAX

- V

OL_MAX

))/R

L

] * (V

CC_MAX

- V

OL_MAX

) =

[(2V - 1.7V)/50

Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

V

OUT

V

CC

V

CC - 2V

Q1

RL

50

Ω