2 / 7 page
CY29943
Document #: 38-07285 Rev. *C
Page 2 of 7
Note:
1.
PD = internal pull-down, PU = internal pull-up.
Pin Description[1]
Pin
Name
PWR
I/O
Description
5
PECL_CLK
I, PU
PECL Input Clock
6
PECL_CLK#
I, PD
PECL Input Clock
3
OE
I, PU
Output Enable. When HIGH, all the outputs are enabled. When set
LOW, the outputs are at high impedance.
9, 10, 11, 13,
14, 15, 18, 19,
20, 22, 23, 24,
26, 27, 28, 30,
31, 32
Q(17:0)
VDD
O
Clock Outputs
7, 8, 16, 21, 29
VDD
3.3V or 2.5V Power Supply
1, 2, 12, 17, 25
VSS
Common Ground
4NC
No Connection
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
