Nexperia

74HC166; 74HCT166

8-bit parallel-in/serial out shift register

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 9.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

RL = Load resistance.

S1 = Test selection switch

Fig. 11. Test circuit for measuring switching times

Table 9. Test data

Input

Load

S1 position

Type

VI

tr, tf

CL

RL

tPHL, tPLH

74HC166

VCC

6 ns

15 pF, 50 pF

1 kΩ

open

74HCT166

3 V

6 ns

15 pF, 50 pF

1 kΩ

open

74HC_HCT166

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 5 — 9 August 2021

12 / 17