DS700DB1

13

CDB53L21

3. HARDWARE MODE CONTROL

The CDB may be configured without the use of a software control port through the use of two switches, “FPGA H/W

Control” and “CS53L21 H/W Control.” These switches are enabled in Hardware Mode only and ignored in Software

Mode. The CDB53L21 automatically enters Hardware Mode upon initial power up, or when exiting Software Mode,

by terminating the Cirrus FlexGUI software or by disconnecting the RS-232 serial cable or USB cable.

3.1

FPGA H/W Control

The “FPGA H/W Control” switch S3 sets up the CDB in 4 pre-defined routing topologies in Hardware Mode.

The tables and figures below describe each switch setting. The At-A-Glance Controls table provides a quick

reference for all presets.

Notes:

1.

H/W Control” switch S5. These settings must be made manually by the user and have to be consistent.

At-A-Glance Controls

S[3:2]

S[1] (See Note 1.)

S[0]

00 - Reserved

0 - CS53L21 Slave Routing

1 - CS53L21 Master Routing

0 - No Loopback Routing

1 - Reserved

01 - I/O Header MCLK / I/O Header clocks/data route through

FPGA

10 - Oscillator MCLK / I/O Header clocks/data route through FPGA

11 - Reserved

Signal

Routing

S[3:0]

General Description

Detailed Description

0

0000

Reserved

1

0001

Reserved

2

0010

Reserved

3

0011

Reserved

I/O MCLK

4

Figure 6

0100

I/O Clocks/Data

1) I/O masters MCLK. 2) I/O masters PCM clocks.

3) SDOUT to CS8406 and I/O Header

5

0101

Reserved

6

Figure 7

0110

CS53L21 Clocks, I/O Data

1) I/O masters MCLK. 2) CS53L21 masters PCM clocks.

3) SDOUT to CS8406 and I/O Header

7

0111

Reserved

Oscillator MCLK

8

Figure 8

1000

I/O Clocks/Data

1) Oscillator masters MCLK. 2) I/O masters PCM clocks.

3) SDOUT to CS8406 and I/O Header

9

1001

Reserved

10

Figure 9

1010

CS53L21 Clocks, I/O Data

1) Oscillator masters MCLK. 2) CS53L21 masters PCM clocks.

3) SDOUT to CS8406 and I/O Header

11

1011

Reserved

12-15 Reserved

Table 1. MCLK and Clock/Data Routing Options