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CS4412 データシート(PDF) 18 Page - Cirrus Logic |
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CS4412 データシート(HTML) 18 Page - Cirrus Logic |
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18 / 22 page ![]() 18 DS749A1 CS4412 5. POWER SUPPLY, GROUNDING, AND PCB LAYOUT 5.1 Power Supply and Grounding The CS4412 requires careful attention to power supply and grounding arrangements if its potential perfor- mance is to be realized. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. It is necessary to decouple the power supply by placing capacitors directly between the power and ground of the CS4412. Decoupling capacitors should be as close to the pins of the CS4412 as possible. The lowest value ceramic capacitor should be closest to the pin and should be mount- ed on the same side of the board as the CS4412 to minimize inductance effects. The CRD4412 reference design demonstrates the optimum layout and power supply arrangements. 5.1.1 Integrated VD Regulator The CS4412 includes two internal linear regulators, one from the VD supply voltage to provide a fixed 2.5 V supply to its internal digital blocks, and another from the VD supply voltage to provide a fixed 2.5 V supply to its internal analog blocks. The LVD pin must be set to indicate the voltage present on the VD pin as shown in Table 8 below. The output of the digital regulator is presented on the VD_REG pin and may be used to provide an exter- nal device with up to 3mA of current at its nominal output voltage of 2.5 V. The output of the analog reg- ulator is presented on the VA_REG pin and must only be connected to the bypass capacitors as shown in the typical connection diagrams. If a nominal supply voltage of 2.5 V is used as the VD supply (see the Recommended Operating Condi- tions table on page 5), the VD, VD_REG, and VA_REG pins must all be connected to the VD supply source. In this configuration, the internal regulators are bypassed and the external supply source is used to directly drive the internal digital and analog sections. 5.2 QFN Thermal Pad The CS4412 is available in a compact QFN package. The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of thermal vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. The CRD4412 reference design demonstrates the optimum thermal pad and via configuration. LVD Indicated VD Supply Level Low 2.5 V or 3.3 V Nominal High 5 V Nominal Table 8. VD Supply Level Indication |
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