MPQ2169B

– 6V, DUAL 1.4A/1.4A OR 2A/0.8A SYNC BUCK REGULATOR, AEC-Q100

MPQ2169B Rev. 1.0

MonolithicPower.com

4

12/20/2021

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PIN FUNCTIONS

Pin #

Name

Description

1

PG2

Power good indicator for channel 2. The output of PG2 is an open drain. A pull-up

resistor to the power source is required if this pin is used. PG2 is pulled high when VFB2

reaches 90% of the reference voltage (VREF), and is pulled low to GND if VFB2 drops to 82%

of VREF.

2

PGND2

Power ground for channel 2. Connect PGND2 to the negative terminals of the input and

output capacitors with larger copper areas. PGND2 must be connected to PGND1

externally on the board.

3

SW2

Switch-node connection to the inductor for channel 2. SW2 connects to the internal

high-side MOSFETs (HS-FETs) and low-side MOSFETs (LS-FETs) of the channel 2 buck

converter.

4

VIN2

Input supply for channel 2. Place a decoupling capacitor to ground, close to VIN2, to

reduce switching spikes.

5

SS2

Soft start for channel 2. Place a capacitor from SS2 to GND to set the soft-start time (tSS)

externally. Floating this pin activates the internal default 0.5ms soft-start setting.

6

FB2

Feedback for channel 2. FB2 is the input to the error amplifier (EA) of channel 2. An

external resistor divider connects FB2 between the output and ground. The voltage on FB2

is compared to the internal 0.6V VREF to set the regulation voltage for channel 2.

7

AGND

Analog ground. Connect AGND to PGND1 and PGND2 externally on the board.

8

VCC

Power supply to the internal regulator for both channels. Decouple VCC with a 0.1µF

to 1µF capacitor, placed between VCC and AGND. Connect VIN1, VIN2, and VCC

together externally. It is not recommended to power them from a separate power supply.

9

FREQ

Frequency set. Connect a resistor to GND to set the switching frequency (fSW).

10

FB1

Feedback for channel 1. FB1 is the input to the EA of channel 1. An external resistor

divider connects FB1 between the output and GND. The voltage on FB1 is compared to

the internal 0.6V VREF to set the regulation voltage for channel 1.

11

SS1

Soft start for channel 1. Place a capacitor from SS1 to GND to set tSS externally. Floating

this pin activates the internal default 0.5ms soft-start setting.

12

VIN1

Input supply for channel 1. Place a decoupling capacitor to ground, close to VIN1, to

reduce switching spikes.

13

SW1

Switch-node connection to the inductor for channel 1. SW1 connects to the internal

HS-FETs and LS-FETs of the channel 1 buck converter.

14

PGND1

Power ground for channel 1. Connect PGND1 to the negative terminals of the input and

output capacitors with larger copper areas. PGND1 must be connected to PGND2

externally on the board.

15

PG1

Power good for channel 1. The output of PG1 is an open drain. A pull-up resistor to the

power source is required if this pin is used. PG1 is pulled high when VFB1 reaches 90% of

VREF, and is pulled low to GND if VFB1 drops to 82% of VREF.

16

EN1

Enable control for channel 1. Pull EN1 below the specified threshold (0.8V) to shut down

the chip. Pull EN above the threshold (0.9V) to enable the chip. Do not float EN1.

17

SYNC

Frequency sync. fSW can be synchronized by an external clock via the SYNC pin.

18

EN2

Enable control for channel 2. Pull EN2 below the specified threshold (0.8V) to shut down

the chip. Pull EN above the threshold (0.9V) to enable the chip. Do not float EN2.