HT48R02 datasheet(13/38 Pages) HOLTEK

13 / 38 page

HT48R01/HT48R02/HT48R03

Rev. 1.00

December 20, 2006

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

The WDT overflow under normal operation will initialise

²chip reset² and set the status bit ²TO². But in the

HALT mode, the overflow will initialise a

²warm reset²,

and only the Program Counter and SP are reset to zero.

To clear the contents of WDT (including the WDT

prescaler), three methods are adopted; external reset (a

low level to RES), software instruction and a

²HALT² in-

struction. The software instruction include

²CLR WDT²

and the other set

-²CLR WDT1² and ²CLR WDT2².Of

these two types of instruction, only one can be active de-

pending on the option

-²CLR WDT times selection op-

tion

².Ifthe ²CLR WDT² is selected (i.e. CLRWDT times

equal one), any execution of the

²CLR WDT² instruction

will clear the WDT. In the case that

²CLR WDT1² and

²CLR WDT2² are chosen (i.e. CLRWDT times equal

two), these two instructions must be executed to clear

the WDT; otherwise, the WDT may reset the chip as a

result of time-out.

The WDT control register contains 4 bits of WDT enable

bits. WDT can be enable by either WDT mask option or

WDT control register (WDTEN[3:0]=0101B) and be dis-

able by both being disable.

Bit No.

Label

Function

0~3

WDTEN0~

WDTEN3

Bit3~0, WDTEN3~WDTEN0=

1010B: WDT disable

others: enable (using 0101B to

enable WDT is strongly recom-

mended for the highest noise im-

munity)

4~5

Unused bit, read as

²0²

Bit No.

Label

Function

6~7

INTES0~

INTES1

External interrupt edge selection

(default=10)

00: disable

01: rising edge trigger

10: falling edge trigger

11: dual edge trigger

WCON (17H) Register

Power Down Operation

- HALT

The HALT mode is initialised by the

²HALT² instruction

and results in the following...

· The system oscillator will be turned off but the WDT

oscillator keeps running (if the WDT oscillator is se-

lected).

· The contents of the on chip RAM and registers remain

unchanged.

· WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

· All of the I/O ports maintain their original status.

· The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialisation and the WDT overflow per-

forms a

²warm reset². After the TO and PDF flags are

examined, the reason for chip reset can be determined.

The PDF flag is cleared by system power-up or execut-

ing the

²CLR WDT² instruction and is set when execut-

ing the

²HALT² instruction. The TO flag is set if the WDT

time-out occurs, and causes a wake-up that only resets

the Program Counter and Stack Pointer; the others keep

their original status.

Both port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by options. Awakening from an I/O port stimulus,

the program will resume execution of the next instruc-

tion. If it is awakened by an interrupt, two sequences

may happen. If the related interrupt is disabled or the in-

terrupt is enabled but the stack is full, the program will

resume execution at the next instruction. If the interrupt

is enabled and the stack is not full, the regular interrupt

response takes place. If an interrupt request flag is set to

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

R O M

C o d e

O p t i o n

f S Y S / 4

f R T C

W D T O S C

f S

Watchdog Timer

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