K4M28163PH - R(B)E/G/C/F

March 2006

7

Mobile SDRAM

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

NOTES:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next

higher integer.

2. Minimum delay is required to complete write.

3. Maximum burst refresh cycle : 8

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

Parameter

Symbol

Version

Unit

Note

-75

-90

-1L

Row active to row active delay

15

18

18

ns

1

RAS to CAS delay

22.5

24

27

ns

1

Row precharge time

22.5

24

27

ns

1

Row active time

50

50

50

ns

1

100

us

Row cycle time

72.5

74

77

ns

1

Last data in to row precharge

15

ns

2

Last data in to Active delay

tRDL + tRP

-

Last data in to new col. address delay

1

CLK

2

Last data in to burst stop

1

CLK

2

Auto refresh cycle time

80

ns

3

Exit self refresh to active command

120

ns

Col. address to col. address delay

1

CLK

4

Number of valid output data

CAS latency=3

2

ea

5

Number of valid output data

CAS latency=2

1

Number of valid output data

CAS latency=1

-

0