RT3662EB datasheet(4/28 Pages) RICHTEK

4 / 28 page

RT3662EB

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS3662EB-04

August

2019

Functional Block Diagram

VIN

TON

GEN

Loop Control

Protection Logic

SVI2 Interface

Configuration Registers

Control Logic

UVLO

PWM

CMP

ADC

PVCC

QR_TH

GND

Driver

PWM1

Current

Balance

IB1

IB2

RGND

Soft-Start &

Slew Rate Control

VSET

ERROR

AMP

From Control Logic

Offset

Cancellation

ISEN1N

ISEN1P

DAC

RAMP

IB1

VREF_PINSET

0.75 x AI_VDDC

ISEN2N

ISEN2P

IB2

IMON

OV/UV

OCP_SPIKE

To Protection Logic

IMONI

1.867m

COMP

VSEN

AI_VDDC

QR_TH

TONSET

OFFSET

PHOCP_TH

TONSET

PWM2

MUX

Driver

POR

LGATEx

PHASEx

UGATEx

BOOTx

Operation

The RT3662EB adopts G-NAVPTM (Green Native AVP)

which is Richtek's proprietary topology derived from

finite DC gain of EA amplifier with current mode control,

making it easy to set the droop to meet all AMD GPU

requirements of AVP (Adaptive Voltage Positioning).

The G-NAVPTM controller is one type of current mode

constant on-time control with DC offset cancellation.

The approach can not only improve DC offset problem

for increasing system accuracy but also provide fast

transient response. When current feedback signal

reaches COMP signal, it generates an on-time width to

achieve PWM modulation.

MUX and ADC

The MUX supports the inputs from SET1, TSEN,

IMONI and VSEN. The ADC converts these analog

signals to digital codes for reporting or performance

adjustment.

SVI2 Interface/Configuration Registers/Control

Logic

The SVI2 interface uses the SVC, SVD, and SVT pins

to communicate with GPU. The configuration registers

save the digital data from ADC output for reporting or

performance adjustment. The Control Logic controls

the ADC timing and generates the digital code of the

VID for VSEN voltage.

Loop Control Protection Logic

Loop control protection logic detects EN and UVLO

signals to initiate the soft-start function, and the

PGOOD and VRHOT_L will be controlled after the

soft-start is finished. When VRHOT indication event

occurs, the VRHOT_L pin voltage will be pulled low.

DAC

The DAC receives VID codes from the SVI2 control

logic to generate an internal reference voltage (VSET)

for controller.

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