IP101GRI datasheet(44/65 Pages) ETC

44 / 65 page

IP101G

Data Sheet

Reduced Media Independent Interface (RMII) is defined to provide a fewer pins data transmission

condition. The management interface, MDC and MDIO, are identical to the MII defined in IEEE 802.3.

RMII supports 10/100Mb data rates and the clock source are provided by a single 50MHz clock from

either external or within IP101G. This clock is used as reference for transmit, receive and control. RMII

provides independent 2 bit wide transmit and receive data path, i.e., TXD[1:0] and RXD[1:0]. CRS_DV is

asserted when the receive medium is not idle and de-asserted when the medium is idle.

Before any transmission occurs, CRS_DV should be de-asserted and value “00” should be present in

both TXD[1:0] and RXD[1:0]. When transmission begins, IP101G will send “01” (TXD[1:0] = 01) for

preamble to indicate SFD, and also assert TX_EN synchronous with first nibble of the preamble. TX_EN

should be de-asserted until the end of the data transmission. At receiving mechanism, by receiving “01”

means a valid data is available. If the False carrier is detected, RXD[1:0] shall be “10” until the end of the

transmission. The MDI transmitter of IP101G can not enter low power idle (LPI) state, but can receive the

LPI signal from MDI path.

At 10Mbps mode, every 10

th cycle of REF_CLK will be sampled in RXD[1:0] and TXD[1:0], because the

REF_CLK frequency is 10 times faster than the data rate of the 10Mbps.

Figure 8 IP101G RMII Mode with internal clock Block Diagram

Figure 9 IP101G RMII Mode with external clock Block Diagram

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January 14, 2014

IP101G-DS-R01

IP101GRI データシート(PDF) 44 Page - List of Unclassifed Manufacturers