MP8792 – 16V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER

MP8792 Rev. 1.0

www.MonolithicPower.com

16

12/2/2019

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© 2019 MPS. All Rights Reserved.

After 200ns, the LS-FET turns on again. The

MP8792 repeats this operation to discharge the

over-voltage on the output. The device exits this

mode when VFB drops below 105% of VREF.

Over-Temperature Protection (OTP)

The MP8792 has over-temperature protection

(OTP).

The

IC

monitors

the

junction

temperature

internally.

If

the

junction

temperature

exceeds

the

threshold

value

(typically 160°C), the converter shuts off and

discharges the TRK/REF capacitors. This is a

non-latch protection. There is about 30°C

hysteresis.

Once

the

junction

temperature

drops to about 130°C, a soft start is initiated.

The OTP function is effective once the MP8792

is enabled.

Output Voltage Setting and Remote Output

Voltage Sensing

First, choose a value for R1. Then R2 can be

calculated with Equation (4):

REF

21

O

REF

V

R (k )

R (k )

VV

 







(4)

To optimize the load transient response, a feed-

forward capacitor (CFF) is recommended in

parallel with R1. R1 and CFF add an extra zero

frequency (fZ) to the system, which improves

loop response. R1 and CFF are selected so that

the zero frequency formed by R1 and CFF is

between 20kHz and 60kHz. The extra zero

frequency can be estimated with Equation (5):

Z

FF

1

f

2

R1 C







(5)

Power Good (PGOOD)

The MP8792 has a power good (PGOOD)

output.

PGOOD

is the

open

drain

of

a

MOSFET. Connect PGOOD to VCC or another

external voltage source (below 3.6V) through a

pull-up resistor (typically 10

kΩ). After applying

the input voltage, the MOSFET turns on, so

PGOOD is pulled to GND before TRK/REF is

ready. After VFB reaches 92.5% of VREF and

a .08ms delay, PGOOD is pulled high.

When VFB drops to 80% of VREF or exceeds

116% of the nominal VREF, PGOOD is latched

low. PGOOD can only be pulled high again

after a new soft start.

If the input supply fails to power the MP8792,

PGOOD is clamped low even though PGOOD

is tied to an external DC source through a pull-

up resistor. Figure 5 shows the relationship

between the PGOOD voltage and the pull-up

current.

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0.6

0.7

0.8

0.9

V_PG (V)

Figure 5: PGOOD Clamped Voltage vs. Pull-Up

Current

EN Configuration

The MP8792 turns on when EN goes high, and

it turns off when EN goes low. Do not float EN.

EN can be driven by an analog or digital control

logic signal to enable or disable the device.

The MP8792 provides accurate EN thresholds,

so a resistor divider from VIN to AGND can

program the input voltage at which the MP8792

is enabled. This is highly recommended for an

application where there is no dedicated EN

control logic signal, to avoid possible UVLO

bouncing during start-up and shutdown. The

resistor divider values can be calculated with

Equation (6):

DOWN

DOWN

UP

EN

START

IN

R

R

R

VIH

V

V







)

(

_

(6)

Where VIHEN is typically 1.22V. RUP and RDOWN

should be chosen so that VEN does not exceed

3.6V when VIN reaches its maximum value.

EN can be directly connected to VIN through a

pull-up resistor (RUP). RUP should be chosen so

that the maximum current going to EN is 50

μA.

RUP can be estimated with Equation (7):

)

(

05

.

0

)

(

)

(

mA

V

VIN

k

R

MAX

UP





(7)