ADFS7124-8BBCPZ datasheet(40/93 Pages) AD

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Data Sheet

ADFS7124-8

GETTING STARTED

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Rev. 0 | 40 of 93

ADC Setups

The ADFS7124-8 has eight independent setups. Each setup con-

sists of the following four registers:

►

Configuration register

►

Filter register

►

Offset register

►

Gain register

For example, Setup 0 consists of Configuration Register 0, Filter

is selectable from the channel registers detailed in the Channel

Configuration section. This allows each channel to be assigned to

one of eight separate setups.

Configuration Registers

The configuration registers allow the user to select the output

coding of the ADC by selecting between bipolar and unipolar. In

bipolar mode, the ADC accepts negative differential input voltages,

and the output coding is offset binary. In unipolar mode, the ADC

accepts only positive differential voltages, and the coding is straight

binary. In either case, the input voltage must be within the AVDD

and AVSS supply voltages. The user can also select the reference

source using these registers. Four options are available: an inter-

nal 2.5 V reference, an external reference connected between RE-

FIN1(+) and REFIN1(−), an external reference connected between

REFIN2(+) and REFIN2(−), or AVDD to AVSS. The PGA gain is also

set; gains of 1, 2, 4, 8, 16, 32, 64, and 128 are provided. The

analog input buffers and reference input buffers for the setup can

also be enabled using this register.

Filter Registers

The filter registers select which digital filter is used at the output

of the ADC modulator. The filter type and the output data rate are

selected by setting the bits in this register. For more information,

see the Digital Filter section.

Offset Registers

The offset registers hold the offset calibration coefficient for the

ADC. The power-on reset value of an offset register is 0x800000.

The offset registers are 24-bit read/write registers. The power-on

reset value is automatically overwritten if an internal or system

zero-scale calibration is initiated by the user or if the offset registers

are written to by the user.

Gain Registers

The gain registers are 24-bit registers that hold the gain calibration

coefficient for the ADC. The gain registers are read/write registers.

The gain is factory calibrated at a gain of 1; thus, the default value

varies from device to device. The default value is automatically

overwritten if an internal or system full-scale calibration is initiated

by the user. For more information on calibration, see the Calibration

section.

Figure 69. ADC Setup Register Grouping

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