データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

Preview PDF HTML

CC2550-RTY1 データシート(PDF) 14 Page - Texas Instruments

Click here to check the latest version.
部品番号 CC2550-RTY1
部品情報  Single Chip Low Cost Low Power RF Transmitter
PDF  55 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
Logo TI - Texas Instruments

CC2550-RTY1 データシート(HTML) 14 Page - Texas Instruments

Back Button CC2550-RTY1 Datasheet HTML 10Page - Texas Instruments CC2550-RTY1 Datasheet HTML 11Page - Texas Instruments CC2550-RTY1 Datasheet HTML 12Page - Texas Instruments CC2550-RTY1 Datasheet HTML 13Page - Texas Instruments CC2550-RTY1 Datasheet HTML 14Page - Texas Instruments CC2550-RTY1 Datasheet HTML 15Page - Texas Instruments CC2550-RTY1 Datasheet HTML 16Page - Texas Instruments CC2550-RTY1 Datasheet HTML 17Page - Texas Instruments CC2550-RTY1 Datasheet HTML 18Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 14 / 55 page
background image
CC2550
PRELIMINARY Data Sheet (Rev.1.2)
SWRS039A
Page 14 of 54
0
A6
A5
A4
A3
A2
A0
A1
D
W
7
D
W
6
D
W
5
D
W
4
D
W
3
D
W
2
D
W
1
D
W
0
1
A6
A5
A4
A3
A2
A0
A1
D
R
7
D
R
6
D
R
5
D
R
4
D
R
3
D
R
2
D
R
1
D
R
0
Read from register:
Write to register:
Hi-Z
X
SCLK:
CSn:
SI
SO
SI
SO
Hi-Z
t
sp
t
ch
t
cl
t
sd
t
hd
t
ns
X
X
Hi-Z
X
S7
S6
S5
S4
S3
S2
S1
S0
Hi-Z
S7
S6
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
S7
X
Figure 6: Configuration registers write and read operations
Parameter
Description
Min
Max
Units
SCLK
frequency
100 ns delay inserted between address byte and data byte (single access), or between
address and data, and between each data byte (burst access).
-
10
MHz
SCLK
frequency, single access
No delay between address and data byte
9
MHz
fSCLK
SCLK
frequency, burst access
No delay between address and data byte, or between data bytes
6.5
MHz
tsp,pd
CSn
low to positive edge on SCLK, in power-down mode
200
-
µs
tsp
CSn
low to positive edge on SCLK, in active mode
20
-
ns
tch
Clock high
50
-
ns
tcl
Clock low
50
-
ns
trise
Clock rise time
-
5
ns
tfall
Clock fall time
-
5
ns
Single access
55
-
ns
tsd
Setup data (negative SCLK edge) to
positive edge on SCLK
(tsd applies between address and data bytes, and
between data bytes)
Burst access
76
-
ns
thd
Hold data after positive edge on SCLK
20
-
ns
tns
Negative edge on SCLK to CSn high
20
-
ns
Table 14: SPI interface timing requirements
Figure 7: Register access types



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか？  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com