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WM8581 データシート(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8581 データシート(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 100 page  WM8581 Production Data w PD Rev 4.0 April 2007 30 DSP MODE B In DSP Mode B, the MSB of Channel 1 left data is sampled on the first BCLK rising edge following a LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2, 3 and 4 follow as shown in Figure 20. Figure 20 DSP Mode B Timing Diagram – PAIF Receiver Input Data Figure 21 DSP Mode B Timing Diagram – SAIF Receiver Input Data The MSB of the output data changes on the same falling edge of BCLK as the low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with the left channel data. Figure 22 DSP Mode B Timing Diagram – PAIF/SAIF Transmitter Data |
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