®

LSN2 Series

Non-isolated, DOSA-SIP, 6/10/16A Selectable-Output DC/DC Converters

www.cd4power.com

These diagrams illustrate the time and slew rate relationship between two

typical power output voltages. Generally the Master will be a primary power

voltage in the system which must be present first or coincident with any

Slave power voltages. The Master output voltage is connected to the Slave’s

Sequence input, either by a voltage divider, divider-plus-capacitor or some

other method. Several standard sequencing architectures are prevalent. They

are concerned with three factors:

For most systems, the time relationship is the dominant factor. The voltage

difference relationship is important for systems very concerned about possible

latchup of programmable devices or overdriving ESD diodes. Lower slew

rates avoid overcurrent shutdown during bypass cap charge-up.

In Figure 18, two POL’s ramp up at the same rate until they reach their dif-

ferent respective final set point voltages. During the ramp, their voltages are

nearly identical. This avoids problems with large currents flowing between

Figures 10 and 11 show both delayed start up and delayed final voltages for

two converters. Figure 10 is called “Inclusive” because the later starting POL

finishes inside the earlier POL. The timing in Figure 10 is more easily built

using a combined digital sequence controller and the Sequence/Track pin.

Figure 11 is the same strategy as Figure 10 but with an “exclusive” timing

relationship staggered approximately the same at power-up and power-down.

Operation

To use the Sequence pin after power start-up stabilizes, apply a rising external

voltage to the Sequence input. As the voltage rises, the output voltage will

track the Sequence input (gain = 1). The output voltage will stop rising

when it reaches the normal set point for the converter. The Sequence input

may optionally continue to rise without any effect on the output. Keep the

Sequence input voltage below the converter’s input supply voltage.

Use a similar strategy on power down. The output voltage will stay constant

until the Sequence input falls below the set point.

Any strategy may be used to deliver the power up/down ramps. The circuits

below show simple RC networks but you may also use operational amplifiers,

D/A converters, etc.

Circuits

The circuits shown in Figures 12 through 14 introduce several concepts when

using these Sequencing controls on Point-of-Load (POL) converters. These

circuits are only for reference and are not intended as final designs ready for

your application. Also, numerous connections are omitted for clarity.

Figure 8. Coincident or Simultaneous Phasing (Identical Slew Rates)

Figure 10. Staggered or Sequential Phasing—Inclusive (Fixed Delays)

Figure 11. Staggered or Sequential Phasing—Exclusive

(Fixed Cascaded Delays)

logic systems which are not initialized yet. Since both end voltages are differ-

ent, each converter reaches it’s setpoint voltage at a different time.

Figure 9 shows two POL’s with different slew rates in order to reach differing

final voltages at about the same time.