AT89LP4052-20PI datasheet(44/90 Pages) ATMEL

44 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

Figure 18-3. SPI Shift Register Diagram

18.3

Serial Clock Generator

The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate =

baud rate) bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possi-

ble clock rates when the SPI is in master mode. In slave mode, the SPI will operate at the rate of

the incoming SCK as long as it does not exceed the maximum bit rate. There are also four pos-

sible combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL

determine which format is used for transmission. The SPI data transfer formats are shown in

Figures 18-4 and and 18-5. To prevent glitches on SCK from disrupting the interface, CPHA,

CPOL, and SPR should be set up before the interface is enabled, and the master device should

be enabled before the slave device(s).

2:1

MUX

2:1

MUX

Serial Master

Serial Slave

LATCH

CLK

LATCH

CLK

LATCH

CLK

LATCH

CLK

Parallel Slave

(Read Buffer)

Parallel Master

(Write Buffer)

Serial Out

Receive

Byte

Serial In

Transmit

Byte

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