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AT89C51CC02CA-RATUM データシート(PDF) 100 Page - ATMEL Corporation |
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AT89C51CC02CA-RATUM データシート(HTML) 100 Page - ATMEL Corporation |
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100 / 156 page  100 AT/T89C51CC02 4126J–CAN–05/06 Table 64. CANIE Register CANIE (S:C3h) – CAN Enable Interrupt message object Registers Reset Value = xxxx 0000b Table 65. CANBT1 Register CANBT1 (S:B4h) – CAN bit Timing Registers 1 Note: 1. The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0. See Figure 41. No default value after reset. 76 54 32 1 0 - - - - IECH 3 IECH 2 IECH 1 IECH 0 Bit Number Bit Mnemonic Description 7 - 4 - Reserved The values read from these bits are indeterminate. Do not set these bits. 3 - 0 IECH3:0 Enable Interrupt by Message Object 0 - disable IT. 1 - enable IT. IECH3:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2. 76 54 32 1 0 - BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - 1 BRP5:0 Baud Rate Prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing.(1) 0- Reserved The value read from this bit is indeterminate. Do not set this bit. Tscl = BRP[5..0] + 1 FCAN |
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