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IP80C88 データシート(PDF) 19 Page - Intersil Corporation

部品番号 IP80C88
部品情報  CMOS 8/16-Bit Microprocessor
PDF  32 Pages
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メーカー  INTERSIL [Intersil Corporation]
ホームページ  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

IP80C88 データシート(HTML) 19 Page - Intersil Corporation

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19
FIGURE 23. BUS TIMING - MINIMUM MODE SYSTEM (Continued)
NOTES:
11. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for
the second INTA cycle.
12. Signals at 82C84A are shown for reference only.
Waveforms (Continued)
T4
T3
T2
T1
TW
TDVCL
TCLDX1 (7)
TWHDX
TCVCTX
TCHCTV (30)
TCLAV
TCLAZ
TCHCTV
(31) TCVCTX
TCVCTV
(17)
(26)
(27)
(29) TCVCTV
DATA OUT
AD7-AD0
INVALID ADDRESS
CLK (82C84A OUTPUT)
WRITE CYCLE
AD7-AD0
DEN
WR
INTA CYCLE
(NOTE 11)
RD, WR = VOH
AD7-AD0
DT/R
INTA
DEN
AD7-AD0
SOFTWARE
HALT -
DEN, RD,
WR, INTA = VOH
SOFTWARE HALT
(29) TCVCTV
POINTER
TCL2CL1
(5)
TW
TCLAV
TCLDV
TCLAX
(18)
TCLDX2
(29)
(28)
TWLWH
(38)
(29) TCVCTV
(19)
TCVCTX
(31)
(6)
(30)
(31)
(17)
TCH1CH2
(4)
ALE
IO/M
DT/R
SSO
TCLLH
(23)
TCHLL
(24)
TCVCTX
(31)
TCHCTV
(30)
80C88



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