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EMC6D103 データシート(PDF) 21 Page - SMSC Corporation |
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EMC6D103 データシート(HTML) 21 Page - SMSC Corporation |
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21 / 92 page  Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features Datasheet SMSC EMC6D103 21 Revision 0.3 (03-01-07) DATASHEET Note: The INT# signal is an alternate function on the PWM2 and TACH3 pins. The EMC6D103 device will respond to the SMBus Alert Response address even if the INT# signal is not selected as the alternate function on one of these pins as long as the following conditions exist: the INTEN bit (register 7Ch bit 2) is set, an individual status bit is set in one of the interrupt status registers, and the corresponding group enable bit is set. Each interrupt event must be enabled into the interrupt status registers, and the status bits must be enabled onto the INT# signal via the group enable bits for each type of event (i.e., temperature, voltage and fan). See the section titled Interrupt Status Registers on page 25. |
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