AM29BDS643G datasheet(45/49 Pages) AMD

部品番号	AM29BDS643G

部品情報	64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory

PDF	49 Pages

Scroll/Zoom	100%

メーカー	AMD [Advanced Micro Devices]

ホームページ	http://www.amd.com

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45 / 49 page

May 8, 2006 25692A2

Am29BDS643G

D A TA

SH EE T

AC CHARACTERISTICS

Note: Devices should be programmed with wait states as discussed in the “Programmable Wait State” section on page 10.

Figure 20.

Initial Access with Power Saving (PS) Function and Address Boundary Latency

Note: If tAVDSM > 1 CLK cycle, wait state usage is reduced. Figure shows 40 MHz clock, handshaking enabled. Wait state usage

is 4 clock cycles instead of 5. Note that tAVDSM must be less than 76 µs for burst operation to begin.

Figure 21.

Example of Extended Valid Address Reducing Wait State Usage

CLK

AVD#

RDY

Address

High-Z

A/DQ0:

A/DQ15

OE#

PS1

PS2

device is programmable from 2 to 7 total cycles

during initial access (here, programmable wait state

function is set to 04h; 6 cycles total)

PS high if data is inverted,

low if data is not inverted

2 additional

wait states if

address is

at boundary

1 additional

wait state to

indicate PS

is enabled

AVD# low with clock

present enables

burst read mode

Address

A16:A21

boundary

latency

tOE

CLK

AVD#

RDY

High-Z

A/DQ

OE#

CE#

tIACC2

tAVDSM

Addresses

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