USB2227_06 datasheet(17/27 Pages) SMSC

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4th Generation USB2.0 Flash Media Controller with Integrated Card Power FETs

Datasheet

SMSC USB2227/USB2228

Revision 1.91 (10-13-06)

DATASHEET

MA2/

SEL_CLKDR

118

A59

I/O8PD

Memory Address Bus:

MA2 Addresses memory locations within the external

memory.

SEL_CLKDRV. During nRESET assertion, this pins will

select the operating clock mode (crystal or externally

driven clock source), and a weak pull-down resistor is

enabled. When nRESET is negated, the value will be

internally latched and this pin will revert to MA2

functionality, the internal pull-down will be disabled.

‘0’ = Crystal operation (24MHz only)

‘1’ = Externally driven clock source (24MHz or 48MHz)

Note:

If the latched value is ‘1’, then the MA2 pin is

tri-stated when the following conditions are

true:

1. IDLE bit (PCON.0) is 1.

2. INT2 is negated

3. SLEEP bit of CLOCK_SEL is 1.

If the latched value is ‘0’, then the MA2 pin will function

identically to the MA[15:3] pins at all times (other than

during nRESET assertion).

MA[1:0]/CLK_

SEL[1:0]

117

116

B55

A58

I/O8PD

Memory Address Bus:

MA[1:0], These signals address memory locations within

the external memory.

SEL[1:0]. During nRESET assertion, these pins will

select the operating frequency of the external clock, and

the corresponding weak pull-down resistors are enabled.

When nRESET is negated, the value on these pins will

be internal latched and these pins will revert to MA[1:0]

functionality, the internal pull-downs will be disabled.

SEL[1:0] = ‘00’. 24MHz

SEL[1:0] = ‘01’. RESERVED

SEL[1:0] = ‘10’. RESERVED

SEL[1:0] = ‘11’. 48MHz

Note:

If the latched value is ‘1’, then the

corresponding MA pin is tri-stated when the

following conditions are true:

1. IDLE bit (PCON.0) is 1.

2. INT2 is negated

3. SLEEP bit of CLOCK_SEL is 1.

If the latched value is ‘0’, then the corresponding MA pin

will function identically to the MA[15:3] pins at all times

(other than during nRESET assertion).

nMWR

Memory Write Strobe:

Program Memory Write; active low

nMRD

Memory Read Strobe:

Program Memory Read; active low

SYMBOL

128-PIN

VTQFP

124-PIN

DQFN

BUFFER

TYPE

DESCRIPTION

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