データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

COM20019IP データシート(PDF) 66 Page - SMSC Corporation

部品番号 COM20019IP
部品情報  Low Cost ARCNET (ANSI 878.1) Controller with 2K x 8 On-Board RAM
PDF  81 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  SMSC [SMSC Corporation]
ホームページ  http://www.smsc.com
Logo SMSC - SMSC Corporation

COM20019IP データシート(HTML) 66 Page - SMSC Corporation

Back Button COM20019IP Datasheet HTML 62Page - SMSC Corporation COM20019IP Datasheet HTML 63Page - SMSC Corporation COM20019IP Datasheet HTML 64Page - SMSC Corporation COM20019IP Datasheet HTML 65Page - SMSC Corporation COM20019IP Datasheet HTML 66Page - SMSC Corporation COM20019IP Datasheet HTML 67Page - SMSC Corporation COM20019IP Datasheet HTML 68Page - SMSC Corporation COM20019IP Datasheet HTML 69Page - SMSC Corporation COM20019IP Datasheet HTML 70Page - SMSC Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 66 / 81 page
background image
66
DISCONTINUED DATASHEET
Data Hold from nWR High
nWR Low Width
nWR High Width
nRD
to nWR Low
A0-A2
VALID DATA
VALID
D0-D7
nCS
t6
t1
t7
t2
t4
t3
Note 2
nWR
nRD
t10
t8
t9
Note 3
t5**
t5
t1
t3
t5
t6
t7
t8
t9
t10
Parameter
Address Setup to nWR Active
nCS Setup to WR Active
Valid Data Setup to nWR High
min
15
5
10
20
20
20
max
4TARB
*
30***
units
nS
nS
nS
nS
nS
nS
nS
nS
t4
nCS Hold from nWR Inactive
0
nS
t2
Address Hold from nWR Inactive
10
nS
Cycle Time (nWR
to Next
)**
***:
nCS may become active after control becomes active, but the data setup time will now
be 30 nS measured from the later of nCS falling or Valid Data available.
The Microcontroller typically accesses the COM20019 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20019 cycles.
Note 1:
Note 2: Any cycle occurring after a write to the Address Pointer Low Register
requires a minimum of 4TARB from the trailing edge of nWR to the leading edge
of the next nWR.
TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
*
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. Same as the XTAL1 period.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5TARB from the trailing edge of nWR to the
leading edge of the next nWR.
**
Note 3:
Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5TARB from the trailing edge of nRD to the
leading edge of nWR.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com