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DESCRIPTION

APPLICATIONS

CDCVF855

SCAS839A – APRIL 2007 – REVISED MAY 2007

2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

• Spread-Spectrum Clock Compatible

The CDCVF855 is a high-performance, low-skew,

low-jitter,

zero-delay

buffer

that

distributes

a

• Operating Frequency: 60 MHz to 220 MHz

differential

clock

input

pair

(CLK,

CLK)

to

4

• Low Jitter (Cycle-Cycle): ±60 ps (±40 ps at 200

differential pairs of clock outputs (Y[0:3], Y[0:3]) and

MHz)

one differential pair of feedback clock outputs

• Low Static Phase Offset: ±50 ps

(FBOUT, FBOUT). The clock outputs are controlled

by the clock inputs (CLK, CLK), the feedback clocks

• Low Jitter (Period): ±60 ps (±30 ps at 200 MHz)

• 1-to-4 Differential Clock Distribution (SSTL2)

When PWRDWN is high, the outputs switch in phase

• Best in Class for V

and frequency with CLK. When PWRDWN is low, all

outputs are disabled to a high-impedance state

• Operates From Dual 2.6-V or 2.5-V Supplies

(3-state) and the PLL is shut down (low-power

• Available in a 28-Pin TSSOP Package

mode). The device also enters this low-power mode

• Consumes < 100-µA Quiescent Current

when the input frequency falls below a suggested

• External Feedback Pins (FBIN, FBIN) Are Used

detection frequency that is below 20 MHz (typical 10

MHz). An input frequency-detection circuit detects

to Synchronize the Outputs to the Input

the low-frequency condition and, after applying a

Clocks

>20-MHz input signal, this detection circuit turns the

• Meets/Exceeds JEDEC Standard (JESD82-1)

PLL on and enables the outputs.

For DDRI-200/266/333 Specification

• Meets/Exceeds Proposed DDRI-400

and bypassed for test purposes. The CDCVF855 is

Specification (JESD82-1A)

also able to track spread-spectrum clocking for

• Enters Low-Power Mode When No CLK Input

reduced EMI.

Signal Is Applied or PWRDWN Is Low

Because the CDCVF855 is based on PLL circuitry, it

requires a stabilization time to achieve phase-lock of

the PLL. This stabilization time is required following

• DDR Memory Modules (DDR400/333/266/200)

power up. The CDCVF855 is characterized for both

• Zero-Delay Fan-Out Buffer

commercial and industrial temperature ranges.

AVAILABLE OPTIONS

TSSOP (PW)

–40

°C to 85°C

CDCVF855PW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.