SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163

SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163

SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276A – DECEMBER 1994 – REVISED JULY 2000

8

POST OFFICE BOX 655303

timing requirements over recommended operating conditions (unless otherwise noted) (see

Figure 1)

SN54ALS161B

SN54ALS162B

SN54ALS163B

SN74ALS161B

SN74ALS163B

UNIT

MIN

MAX

MIN

MAX

fclock

Clock frequency

22

40

MHz

t

Pulse duration

CLR high or low

20

12.5

ns

tw

Pulse duration

’ALS161B

CLR low

20

15

ns

↑

A, B, C, D

50

15

↑

LOAD

20

15

↑

’ALS161B

ENP ENT

25

15

tsu

Setup time, before CLK

↑

SN54ALS162B, ’ALS163B

ENP, ENT

20

15

ns

’ALS161B

CLR inactive

10

10

SN54ALS162B ’ALS163B

CLR low

20

15

SN54ALS162B, ’ALS163B

CLR high

20

10

th

Hold time, all synchronous inputs after CLK

↑

0

0

ns

switching characteristics over recommended operating conditions (unless otherwise noted) (see

Figure 1)

PARAMETER

FROM

TO

SN54ALS161B

SN74ALS161B

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

MAX

MIN

MAX

UNIT

fmax

22

40

MHz

tPLH

CLK

RCO

5

34

5

20

ns

tPHL

CLK

RCO

5

27

5

20

ns

tPLH

CLK

Any Q

4

19

4

15

ns

tPHL

CLK

Any Q

6

25

6

20

ns

tPLH

ENT

RCO

3

18

3

13

ns

tPHL

ENT

RCO

3

17

3

13

ns

tPHL

CLR

Any Q

8

27

8

24

ns

tPHL

CLR

RCO

11

32

11

23

ns

switching characteristics over recommended operating conditions (unless otherwise noted) (see

Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

SN54ALS162B

SN54ALS163B

SN74ALS163B

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

MIN

MAX

fmax

22

40

MHz

tPLH

CLK

RCO

5

25

5

20

ns

tPHL

CLK

RCO

5

25

5

20

ns

tPLH

CLK

Any Q

4

18

4

15

ns

tPHL

CLK

Any Q

6

25

6

20

ns

tPLH

ENT

RCO

3

16

3

13

ns

tPHL

ENT

RCO

3

16

3

13

ns