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PCF8573P データシート(PDF) 13 Page - NXP Semiconductors |
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PCF8573P データシート(HTML) 13 Page - NXP Semiconductors |
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13 / 24 page ![]() 1997 Mar 28 13 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). 11 HANDLING Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under “Handling MOS Devices”. SYMBOL PARAMETER MIN. MAX. UNIT VDD − VSS1 supply voltage (pin 16 to pin 15) −0.3 +8.0 V VDD − VSS2 supply voltage (pin 16 to pin 8) −0.3 +8.0 V Vl input voltage pins 4 and 5 (with input impedance of minimum 500 Ω)VSS2 − 0.8 VDD + 0.8 V pins 6, 7, 13 and 14 VSS1 − 0.6 VDD + 0.6 V any other pin VSS2 − 0.6 VDD + 0.6 V Il DC input current − 10 mA IO DC output current − 10 mA Ptot total power dissipation per package − 200 mW PO power dissipation per output − 100 mW Tamb operating ambient temperature −40 +85 °C Tstg storage temperature −55 +125 °C |
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