Philips Semiconductors

Product specification

PCK953

50–125 MHz PECL input/CMOS output

3.3 V PLL clock driver

2

2001 Feb 08

853–2222 25600

DESCRIPTION

The PCK953 is a 3.3 V compatible, PLL-based clock driver device

targeted for high performance clock tree designs. With output

frequencies of up to 125 MHz, and output skews of 100 ps, the

PCK953 is ideal for the most demanding clock tree designs. The

devices employ a fully differential PLL design to minimize

cycle-to-cycle and phase jitter.

The PCK953 has a differential LVPECL reference input, along with

an external feedback input. These features make the PCK953 ideal

for use as a zero delay, low skew fanout buffer. The device

performance has been tuned and optimized for zero delay

performance. The MR/OE input pin will reset the internal counters

and 3-State the output buffers when driven HIGH.

The PCK953 is fully 3.3 V compatible and requires no external loop

filter components. All control inputs accept LVCMOS or LVTTL

compatible levels, while the outputs provide LVCMOS levels with the

ability to drive terminated 50

Ω transmission lines. For series

terminated 50

Ω lines, each of the PCK953 outputs can drive two

traces, giving the device an effective fanout of 1:18. The device is

packaged in a 7

× 7 mm 32-lead LQFP package to provide the

optimum combination of board density and performance.

FEATURES

PIN CONFIGURATION

1

2

3

4

5

6

7

FB_CLK

NC

NC

NC

GNDI

NC

8

PECL_CLK

24

23

22

21

20

19

18

Q1

Q2

GNDO

Q3

Q4

17 GNDO

SW00625

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DRAWING NUMBER

plastic low profile quad flat

package; 32 leads

0 to +70

°C

PCK953BD

SOT358-1

LOGIC DIAGRAM

7

PHASE

DETECTOR

PECL_CLK

PECL_CLK

FB_CLK

VCO_SEL

BYPASS

MR/OE

PLL_EN

LPF

VCO

200–500 MHz

B2

B4

QFB

Q0:6

Q7

SW00624