TSL25723FN datasheet(28/41 Pages) OSRAM

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Datasheet, Public

Page 27

[v2-00] 2022-Nov-30

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TSL2572 − Register Overview

Status Register (0x13)

The Status Register provides the internal status of the device.

This register is read only.

Figure 31:

Status Register

ADC Channel Data Registers (0x14 - 0x17)

ALS data is stored as two 16-bit values. To ensure the data is

read correctly, a two-byte read I²C transaction should be used

with auto increment protocol bits set in the command register.

With this operation, when the lower byte register is read, the

upper eight bits are stored in a shadow register, which is read

by a subsequent read to the upper byte. The upper register will

read the correct value even if additional ADC integration cycles

end between the reading of the lower and upper registers.

Figure 32:

ADC Channel Data Registers

Field

Bit

Description

Reserved

7:5

Reserved. Bits read as 0.

AINT

ALS Interrupt. Indicates that the device is asserting an ALS interrupt.

Reserved

3:1

Reserved. Bits read as 0.

AVALID

ALS Valid. Indicates that the ALS channels have completed an

integration cycle after AEN has been asserted.

Address

Bits

Description

C0DATA

0x14

7:0

ALS CH0 data low byte.

C0DATAH

0x15

7:0

ALS CH0 data high byte.

C1DATA

0x16

7:0

ALS CH1 data low byte.

C1DATAH

0x17

7:0

ALS CH1 data high byte.

AVALID

STATUS

Reserved

AINT

Reset

0x00

Reserved

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