TSL2580FN datasheet(30/53 Pages) OSRAM

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ams Datasheet

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[v1-00] 2016-Apr-05

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TSL2580, TSL2581 − Register Set

The upper byte data registers can only be read following a read

to the corresponding lower byte register. When the lower byte

The upper register will read the correct value even if additional

ADC integration cycles end between the reading of the lower

and upper registers.

Note(s): The Read Word protocol can be used to read

byte-paired registers. For example, the DATA0LOW and

DATA0HIGH registers (as well as the DATA1LOW and DATA1HIGH

registers) may be read together to obtain the 16-bit ADC value

in a single transaction

Manual Integration Timer (18h - 19h)

The MANUAL INTEGRATION TIMER registers provide the number

of cycles in 10.9

μs increments that occurred during a manual

start/stop integration period. The timer is expressed as a 16-bit

value across two registers. See Control Register (00h) and

Timing Register (01h) for further instructions in configuring a

manual integration. The maximum time that can be derived

without an overflow is 714.3 ms.

Figure 38:

Manual Integration Timer Registers

TIMER

Address

Bits

Description

TIMERLOW

18h

7:0

Manual Integration Timer lower byte

TIMERHIGH

19h

7:0

Manual Integration Timer upper byte

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