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DSP56374UM/D データシート(PDF) 35 Page - Freescale Semiconductor, Inc |
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DSP56374UM/D データシート(HTML) 35 Page - Freescale Semiconductor, Inc |
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35 / 64 page  Serial Host Interface SPI Protocol Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 35 13 Serial Host Interface SPI Protocol Timing Table 21. Serial Host Interface SPI Protocol Timing No. Characteristics1,3,4 Mode Filter Mode Expression Min Max Unit 23 Minimum serial clock cycle = tSPICC(min) Master/Slave Bypassed 10.0 x TC + 9 76.0 — ns Very Narrow 10.0 x TC + 9 76.0 — ns Narrow 10.0 x TC + 133 200.0 — ns Wide 10.0 x TC + 333 400.0 — ns XX Tolerable Spike width on data or clock in. — Bypassed — — 0 ns Very Narrow — — 10 ns Narrow — — 50 ns Wide — — 100 ns 24 Serial clock high period Master Bypassed — 38.0 — ns Very Narrow — 38.0 — ns Narrow — 100.0 — ns Wide — 200.0 — ns Slave Bypassed 2.0 x TC + 19.6 33.0 — ns Very Narrow 2.0 x TC + 19.6 33.0 — ns Narrow 2.0 x TC + 86.6 100.0 — ns Wide 2.0 x TC + 186.6 200.0 — ns 25 Serial clock low period Master Bypassed — 38.0 — ns Very Narrow — 38.0 — ns Narrow — 100.0 — ns Wide — 200.0 — ns Slave Bypassed 2.0 x TC + 19.6 33.0 — ns Very Narrow 2.0 x TC + 19.6 33.0 — ns Narrow 2.0 x TC + 86.6 100.0 — ns Wide 2.0 x TC + 186.6 200.0 — ns 26 Serial clock rise/fall time Master Slave — — —— — — 5 ns ns — — |
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