SST45LF010_03 datasheet(2/16 Pages) SST

2 / 16 page

Data Sheet

1 Mbit Serial Flash

SST45LF010

S71128-04-000

3/03

372

Reset

Reset will terminate any operation, e.g., Read, Erase and

Program, in progress. It is activated by a high to low tran-

sition on the RST# pin. The device will remain in reset

condition as long as RST# is low. Minimum reset time is

10 µs. See Figure 15 for reset timing diagram. RST# is

internally pulled-up and could remain unconnected dur-

ing normal operation. After reset, the device is in standby

mode, a high to low transition on CE# is required to start

the next operation.

An internal power-on reset circuit protects against acci-

dental data writes. Applying a logic level low to RST# dur-

ing the power-on process then changing to a logic level

high when VDD has reached the correct voltage level will

provide additional protection against accidental writes

during power on.

Read SST ID/Read Device ID

The Read SST ID and Read Device ID operations read the

JEDEC assigned manufacturer’s identification and the manu-

facturer assigned device IDs. These IDs may be used to

determine the actual device resident in the system.

Write Protect

The WP# pin provides inadvertent write protection. The

WP# pin must be held high for any Erase or Program oper-

ation. The WP# pin can be VIL or VIH, but no other value, for

all other operations. In typical use, the WP# pin is con-

nected to VSS with a standard pull-down resistor. WP# is

then driven high whenever an Erase or Program operation

is required. If the WP# pin is tied to VDD with a pull-up resis-

tor, then all operations may occur and the write protection

feature is disabled. The WP# pin has an internal pull-up

and could remain unconnected when not used.

Reduced-Function Option

(SST45LF010-10-4C-SA-DD014)

The SST45LF010-10-4C-SA-DD014 is a reduced-function

option of the SST45LF010-10-4C-xA.

For these devices, SST only tests and guarantees func-

tionality when separate serial input and serial output data

lines are used. Valid connections must be as illustrated in

Figure 1.

The RESET# pin is not tested during production; it must be

left unconnected or tied to VDD.

FIGURE 1: VALID CONNECTIONS FOR

SST45LF010-10-4C-SA-DD014

TABLE

1: PRODUCT IDENTIFICATION

Byte

Data

Manufacturer’s ID

0000H

BFH

Device ID

0001H

42H

T1.2 372

Host Controller

SST45LF010-10-4C-SA-DD014

SCK

372 ILL F21.0

SST45LF010 データシート(PDF) 2 Page - Silicon Storage Technology, Inc

SST45LF010 データシート(HTML) 2 Page - Silicon Storage Technology, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

データシートダウンロード