Philips Semiconductors Programmable Logic Devices

Product specification

PLHS501/PLHS501I

Programmable macro logic

PML

™

October 22, 1993

2

ORDERING INFORMATION

DESCRIPTION

OPERATING CONDITIONS

ORDER CODE

DRAWING NUMBER

52-Pin Plastic Leaded Chip Carrier

Commercial Temperature Range

±5% Power Supply

PLHS501A

0397E

52-Pin Plastic Leaded Chip Carrier

Industrial Temperature Range

±10% Power Supply

PLHS501IA

0397E

DESIGN DEVELOPMENT TOOLS

SNAP

The SNAP Software Development System

provides the necessary tools for designing

with PML. SNAP provides the following:

third-party schematic design packages

such as OrCAD/SDT III

FutureNet

and user defined functions

simulation and timing simulation.

SNAP operates on an IBM

PS/2, or any compatible system with DOS

2.1 or higher. The minimum system

configuration for SNAP is 640K bytes of RAM

and a hard disk.

SNAP provides primitive PML function

libraries for third-party schematic design

packages. Custom macro function libraries

can be defined in schematic or equation form.

After the completion of a design, the software

compiles the design for syntax and

completeness. Complete simulation can be

carried out using the different simulation tools

available.

The programming data is generated in

JEDEC format. Using the Device

Programmer Interface (DPI) module of SNAP,

the JEDEC fusemap is sent from the host

computer to the device programmer.

DESIGN SECURITY

The PLHS501 has a programmable security

fuse that controls the access to the data

programmed in the device. By using this

programmable feature, proprietary designs

implemented in the device cannot be copied

or retrieved.

PROGRAMMING/SOFTWARE

SUPPORT

Refer to Section 9

(Development Software)

and Section 10

(Third-party Programmer/

Software Support) of this data handbook for

additional information.

FutureNet is a trademark of FutureNet Corporation.

OrCAD/SDT is a trademark of OrCAD, Inc.

IBM is a registered trademark of International Business Machines Corporation.