MPC885ZP66 datasheet(74/92 Pages) FREESCALE

74 / 92 page

MPC885/MPC880 Hardware Specifications, Rev. 3

Freescale Semiconductor

FEC Electrical Characteristics

Figure 74 shows the MII asynchronous inputs signal timing diagram.

Figure 74. MII Async Inputs Timing Diagram

15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)

Table 37 provides information on the MII serial management channel signal timing. The FEC functions correctly

with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.

Figure 75 shows the MII serial management channel timing diagram.

Figure 75. MII Serial Management Channel Timing Diagram

Table 37. MII Serial Management Channel Timing

Num

Characteristic

Min

Max

Unit

M10

MII_MDC falling edge to MII_MDIO output invalid (minimum

propagation delay)

0—

M11

MII_MDC falling edge to MII_MDIO output valid (max prop delay)

—

M12

MII_MDIO (input) to MII_MDC rising edge setup

—

M13

MII_MDIO (input) to MII_MDC rising edge hold

—

M14

MII_MDC pulse width high

40%

60%

MII_MDC period

M15

MII_MDC pulse width low

40%

60%

MII_MDC period

MII_CRS, MII_COL

M11

MII_MDC (output)

MII_MDIO (output)

M12

M13

MII_MDIO (input)

M10

M14

MM15

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