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MP1530DM データシート(PDF) 9 Page - Monolithic Power Systems |
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MP1530DM データシート(HTML) 9 Page - Monolithic Power Systems |
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9 / 15 page ![]() MP1530 – TRIPLE OUTPUT STEP-UP PLUS LINEAR REGULATORS FOR TFT BIAS MP1530 Rev. 1.4 www.MonolithicPower.com 9 5/19/2006 MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2006 MPS. All Rights Reserved. The positive linear regulator (GH) is then soft- started and allowed to settle in one period of CT ramp. Nine periods of the CT ramp have occurred since the chip enabled. If all outputs are in regulation (>80%), the CT will stop ramping and be held at ground. The RDY pin will be pulled down to an active low. If any output remains below regulation (<80%) before and through the nine CT periods, RDY will remain high and CT will begin its fault timer pulse. START 3 START 2 START 1 POWER ON RESET 0V 0V 0V CT EN 0V IN 1.25V VIN VEN HIGH VIN VIN VMAIN VGL VGH OUTPUT VOLTAGES TIME RDY 0V Figure 2—Startup Timing Diagram |
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