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SC2000 データシート(PDF) 29 Page - NXP Semiconductors |
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SC2000 データシート(HTML) 29 Page - NXP Semiconductors |
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29 / 44 page  2000 Sep 07 29 Philips Semiconductors Preliminary specification Universal Timeslot Interchange SC2000 Table 8. Local Bus Interface Timing — PEB Resource Module With Switching Symbol Parameter Min Typ Max Unit t1a CLKR high time (1.544 Mbps) 323 ns t1b CLKR high time (2.048 Mbps) 244 ns t2a CLKR low time (1.544 Mbps) 323 ns t2b CLKR low time (2.048 Mbps) 244 ns t3a CLKR period (1.544 Mbps) 647 ns t3b CLKR period (2.048 Mbps) 488 ns t4 SO_CLK, SI_CLK ↑ delay from CLKR ↑ 35 ns t5 SO_CLK, SI_CLK ↓ delay from CLKR ↓ 35 ns t6 FSYNCR setup to CLKR ↓ 5 ns t7 FSYNCR hold from CLKR ↓ 15 ns t8 SO_FS, SI_FS ↑delay from FSYNCR ↑ 35 ns t9 SO_FS, SI_FS ↓delay from FSYNCR ↓ 35 ns t10 SO_MS ↑ delay from MSYNCR↑ 35 ns t11 SO_MS ↓ delay from MSYNCR ↓ 35 ns t12 SI_MS ↑ delay from L_MSYNCT↑ 35 ns t13 SI_MS ↓ delay from L_MSYNCT↓ 35 ns t14 SO float to valid delay from CLKR ↑ 40 ns t15 SO valid to valid delay from CLKR ↑ 40 ns t16 SO valid to float delay from CLKR ↑ 25 ns t17 SI setup to CLKR ↓ 0 ns t18 SI hold from CLKR ↓ 25 ns t19 SER enable delay from CLKR ↑ 70 ns t20 SER valid delay from CLKR ↑ 70 ns t21 SER disable delay from CLKR ↑ 70 ns t22 SER setup to CLKR ↓ 0 ns t23 SER hold from CLKR ↓ 25 ns t24 TSX* ↓ delay from CLKR↑ 35 ns t25 TSX* ↑ delay from CLKR↑ 70 ns t26 TSX* setup to CLKR ↓ 0 ns t27 TSX* hold from CLKR ↓ 25 ns Notes: 1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V. 2. SER = L_SERT, SERR, R_SERT, SERT. 3. TSX* = L_TSX*, R_TSX*. |
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