SC28L202 datasheet(39/77 Pages) PHILIPS

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Philips Semiconductors

Objective specification

SC28L202

Dual UART

2000 Feb 10

XISR – Xon–Xoff Interrupt Status Register A and B (Reading this register clears XISR(7:4))

Bits 7:6

Bits 5:4

Bits 3:2

Bits 1:0

Received X Character Status

Automatic X Character transmission

status

TxD flow status

TxD character status

00 = none

01 = Xoff received

10 = Xon received

11 = both received

00 = none

01 = Xon transmitted

10 = Xoff transmitted

11 = Both transmitted

00 = normal transmission

01 = TxD halt pending

10 = re – enabled

11 = flow halted

00 = normal TxD data

01 = Idle wait for FIFO

data

10 = Xoff in pending

11 = Xon in pending

XISR[7:6] Received X Character Status.

This field can be read to determine if the receiver has encountered a

Xon or Xoff character in the incoming data stream. These bits are

maintained until a read of the XISR. The field is updated by X

character reception regardless of the state of MR3(7) and MR3(3:2)

or IMR(4). The field can therefore be used as a character detector

for the bit patterns stored in the Xon and Xoff Character Registers.

XISR[5:4] Automatic transmission Status.

This field indicates the last flow control character sent in the Auto

Receiver flow control mode. If Auto Receiver mode has not been

enabled, this field will always read b’00. It will likewise reset to b’00 if

MR0(3) is reset. If the Auto Receiver mode is exited while this field

reads b’10, it is the user’s responsibility to transmit a Xon, when

appropriate.

XISR[3:2] TxD Condition of the automatic flow control status.

This field tracks the transmitter’s flow status as follows:

• 00 – normal transmission. Transmitter is not affected by Xon or

Xoff.

• 01 – TxD halt pending. After the current character finishes the

transmitter will stop. The status will then change to b’11.

• 10 – re–enabled. The transmitter had been halted and has been

restarted. It is sending (or is prepared to send) data characters.

After a read of the XISR, it will return to ”normal” status.

• 11 – The transmitter is stopped due to an Xoff character being

received from its associated receiver. The transmitter is “flow

controlled”.

XISR[1:0] TxD X character Status.

This field allows determination of the type of character being

transmitted. It will always be b’00 if none of the automatic X

character controls of MR3[3:2] is enabled.

• 01 – The channel is waiting for a data character to transfer from

the TxFIFO. This condition will only occur for a bit time after a Xon

or Xoff character transmission unless the TxFIFO is empty.

• 10 – A command to send an Xoff character is pending.

• 11 – A command to send an Xon character is pending.

Conditions b’10 and b’11 will not exist for more than a character

time.

WCXER Watch Dog, Character, Address and X Enable Register – A and B

Bit 7

Bit 6

Bit 5

Bit 4

BIT 3

BIT 2

BIT 1

BIT 0

Watch dog *

Address recognition

Xon recognition

Xoff Recognition

1 = disable Wd

0 = no action

1 = enable

0 = no action

1 = disable Ar

0 = no action

1 = enable Ar

0 = no action

1 = disable

Xon

0 = no action

1 = enable

Xon

0 = no action

1 = disable

Xoff

0 = no action

1 = enable

Xoff

0 = no action

This register enables the UART’s Character Recognition, Address

Recognition and Receiver watchdog timer. If both enable and

disable are active a disable results. This register is used to enable

the general–purpose character recognition feature WITHOUT

causing any Xon/Xoff or wakeup mode activities to occur. The

recognition event is reported in the ISR register.

* This bit control is duplicated at MR0[7].

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