データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

24LCS21-/P データシート(PDF) 6 Page - Microchip Technology

部品番号 24LCS21-/P
部品情報  1K 2.5V Dual Mode I 2 C Serial EEPROM
PDF  24 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  MICROCHIP [Microchip Technology]
ホームページ  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

24LCS21-/P データシート(HTML) 6 Page - Microchip Technology

Back Button 24LCS21-/P Datasheet HTML 2Page - Microchip Technology 24LCS21-/P Datasheet HTML 3Page - Microchip Technology 24LCS21-/P Datasheet HTML 4Page - Microchip Technology 24LCS21-/P Datasheet HTML 5Page - Microchip Technology 24LCS21-/P Datasheet HTML 6Page - Microchip Technology 24LCS21-/P Datasheet HTML 7Page - Microchip Technology 24LCS21-/P Datasheet HTML 8Page - Microchip Technology 24LCS21-/P Datasheet HTML 9Page - Microchip Technology 24LCS21-/P Datasheet HTML 10Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 24 page
background image
24LCS21
DS21127F-page 6
© 2005 Microchip Technology Inc.
3.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in
first-out (FIFO) fashion.
3.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse.
Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-3:
BUS TIMING START/STOP
FIGURE 3-4:
BUS TIMING DATA
Note:
Once switched into Bidirectional mode,
the 24LCS21 will remain in that mode
until power goes away. Removing power
is the only way to reset the 24LCS21 into
the Transmit-Only mode.
Note:
The 24LCS21 does not generate any
Acknowledge
bits
if
an
internal
programming cycle is in progress.
TSU:STA
THD:STA
VHYS
TSU:STO
Start
Stop
SCL
SDA
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TBUF
TAA
TR



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com